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Silicon Labs /SiM3_NRND /SIM3L166_C /I2C_0 /TIMERRL

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Interpret as TIMERRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0T0RL0T1RL0T2RL0T3RL

Description

Timer Reload Values

Fields

T0RL

Timer Byte 0 Reload / Bus Free Timeout.
T1RL

Timer Byte 1 Reload / SCL High Time.
T2RL

Timer Byte 2 Reload / SCL Low Timeout Bits [11:4].
T3RL

Timer Byte 3 Reload / SCL Low Timeout Bits [19:12].

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data